1. Field of the Invention
The present invention relates to a flip-flop circuit, more particularly relates to a flip-flop circuit capable of preventing a malfunction due to a clock skew.
2. Description of the Related Art
In recent years, the increasing miniaturization of the manufacturing process has led to an increase in the number of the logic circuits. To reduce the power consumption, use is made of many functional clock signals etc. resulting in a tendency for a larger clock skew in the chip. On the other hand, the delay time of the gates becomes smaller so the probability of erroneous operation due to the skew becomes higher.
To prevent an erroneous operation due to the skew in the logic circuit, the delay element of the data is formed so as to occupy a relatively large area. The control thereof also becomes more difficult.
Particularly in a scan flip-flop circuit having input/outputs of two systems of data, at a serial shift operation of a scan test, the serial output signal is directly connected to the serial signal input terminal of the next stage, so it suffers from the disadvantage that the data is propagated fast and therefore malfunction due to the skew is more apt to occur in comparison with the system input.
Arranging the two systems of clocks so as to prevent this makes the arrangement and interconnections excessively difficult and requires the addition of other circuits to the scan flip-flop circuit in order to adjust the timing, so causes a great increase in the chip area.